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NXP Semiconductors /LPC11Cxx /CT16B0 /CCR

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Interpret as CCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DISABLED)CAP0RE 0 (DISABLED)CAP0FE 0 (DISABLED)CAP0I 0RESERVED

CAP0I=DISABLED, CAP0FE=DISABLED, CAP0RE=DISABLED

Description

Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.

Fields

CAP0RE

Capture on CT16Bn_CAP0 rising edge: a sequence of 0 then 1 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC.

0 (DISABLED): Disabled

1 (ENABLED): Enabled
CAP0FE

Capture on CT16Bn_CAP0 falling edge: a sequence of 1 then 0 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC.

0 (DISABLED): Disabled

1 (ENABLED): Enabled
CAP0I

Interrupt on CT16Bn_CAP0 event: a CR0 load due to a CT16Bn_CAP0 event will generate an interrupt.

0 (DISABLED): Disabled

1 (ENABLED): Enabled
RESERVED

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data